A memory controller is a type of circuit that manages the flow of data going into and coming out from a memory device. The memory controller generates the signals necessary to write data to the memory device and to read data from the memory device. In the case of a dynamic random access memory (DRAM), for example, the memory controller is configured to generate signals for storing data within the DRAM, reading data from the DRAM, and refreshing the DRAM as governed by the relevant controlling specification.
In the case of a Double Data Rate (DDR) Synchronous DRAM (SDRAM), data is transferred between the memory controller and the DDR SDRAM on both the rising edge and the falling edge of the clock signal. A memory controller configured to operate with a DDR SDRAM is configured to generate the signals necessary for storing data within the DDR SDRAM, reading data from the DDR SDRAM, and refreshing the DDR SDRAM, to achieve effectively twice the data throughput of a single data rate memory device/memory controller configuration at the same clock rate.
In order for a memory controller to operate reliably, the clock signal used by the memory controller must be properly aligned with the data signals flowing between the memory controller and the memory device to ensure that data is not lost. Typically, signals are aligned through a calibration process that is performed at startup of the IC within which the memory controller is disposed. As the IC continues to operate, however, variations in voltage and temperature can cause the clock signal provided to the memory controller to drift or become misaligned with respect to the data signals exchanged between the memory controller and the memory device. This drift in alignment between clock signal and data signals increases the likelihood of data loss.
Some systems attempt to re-calibrate the clock and data signals to avoid misalignment. Generally, re-calibration is achieved by first stopping operation of the memory controller, performing the calibration process anew, and then restarting operation of the memory controller. Such techniques are undesirable since interrupting operation of the memory controller slows operation of the larger system within which the memory controller is disposed. Further, re-calibration can be a time consuming process when considered in light of the speed at which the memory device/and memory controller configuration can operate.